Adjustable second-order-compensation bandgap reference

ABSTRACT

A voltage reference is produced from PTAT, CTAT, and nonlinear current components generated in isolation from each other and combined to create the voltage reference.

TECHNICAL FIELD

Embodiments of the invention generally relate to voltage references and, more particularly, to bandgap-reference circuits.

BACKGROUND

Many transistor-based electronic circuits will function properly only if they are supplied a very precise power-supply voltage; if the supply voltage drifts too far out of an acceptable tolerance, the transistors it powers may function unpredictably, poorly, or not at all. Many factors may affect the value of the supply voltage, including fluctuations in a power source (e.g., a battery or AC mains supply), changes in temperature, or changes in the load on the power supply. One way that a power supply may maintain a more stable output voltage is to generate a “reference voltage”: a voltage derived from a fixed, stable, and constant value such as (in many transistor-based supplies) the energy bandgap intrinsic to a given material. The energy bandgap of silicon, for example, is approximately 1.11 electron-volts at room temperature, regardless of its power source or loading. Because the energy bandgap is susceptible to changes in temperature, however, a simple reference-voltage generation circuit generates two reference values: a first one that changes in the same direction as a change in the temperature (a so-called proportional-to-absolute-temperature or “PTAT” value) and a second one that changes in the direction opposed to the temperature change (a complementary-to-absolute-temperature or “CTAT” value). The two values are added together and, to first order, the temperature dependencies cancel each other out. FIG. 1A illustrates a simple bandgap-reference circuit 100 that includes a first transistor 102 configured for generating a CTAT value 104 across a first resistor 106 and a second transistor 108 for generating a PTAT value 110 across a second resistor 112. The output value 114 combines the two generated values 104, 110.

As supply voltages have dropped and transistors have become less tolerant of variations, however, the simple bandgap-reference circuit 100 shown in FIG. 1A has proved inadequate in some applications because it does not compensate for second-order effects of temperature on the bandgap value (which are explained in greater detail below). A more sophisticated bandgap-reference circuit 150, shown in FIG. 1B, includes first-order PTAT and CTAT value-generating transistors 152, 154 (analogous to the transistors 102, 108 in the simpler circuit 100 of FIG. 1A) but also includes a third transistor 156 that is configured to generate a second-order temperature factor. The first two transistors 152, 154 generate PTAT and CTAT currents 158, 160 (which are tapped via a buffer 162 and fed back to control current sources 164). A portion of the current 166 generated by the third transistor 156 is subtracted from the PTAT/CTAT currents 158, 160 via resistors 168, 170, thereby accounting for the second-order effects. The output current is mirrored using a current mirror 172, and an output voltage is developed at an output terminal 174 across an output resistor 176.

While the second-order circuit 150 of FIG. 1B improves upon the simpler circuit 100 of FIG. 1A, it is designed based on an approximation of the second-order current 166 that may not always hold true. Specifically, it is assumed that the current 166 generated by the third transistor 156 is not significantly affected by the additional contributions added from the PTAT/CTAT currents 158, 160. In reality, however, this may not always be the case; the third transistor 156 may be calibrated to generate the second-order factor (the “α” factor, as referred to throughout this application) at a particular temperature (for example), but changing conditions may upset the balance of currents flowing into it, producing an error.

Furthermore, the calibration/characterization of the transistors 152, 154, 156 must generally be predetermined by a computer simulation of the circuit 150 because, once manufactured, the circuit 150 cannot be adjusted. The computer model of the transistors 152, 154, 156 may not be accurate enough, however, to precisely determine the value of a process-dependent factor (referred to herein as “XTI” and explained in greater detail below). This XTI parameter may be especially difficult to predict in CMOS processes, in which models of bipolar junction transistors (BJTs) are not well-developed. The actual value of this process-dependent XTI factor (as explained in greater detail below) may thus differ from the simulated or predicted value, further increasing the error of the circuit 150. This error may be unacceptable in some applications; a need therefore exists for an adjustable voltage-reference circuit that correctly and robustly cancels out second-order temperature effects in its generated output.

SUMMARY

Various aspects of the systems and methods described herein include deriving each term of a temperature-independent reference voltage individually (i.e., in isolation from each other) and combining them in a way such that they do not interfere with each other. In one embodiment, the terms are generated as currents and summed together; the resulting summed current is then transformed back into a temperature-independent and second-order-corrected output voltage. The process-dependent XTI factor may be adjusted after manufacture by tuning a resistor ratio to exactly match the measured process factor, thereby overcoming any possible inaccuracy in the BJT simulation models.

In one aspect, a system for generating a voltage reference includes three blocks and an output circuit. The first block generates a proportional-to-absolute-temperature (“PTAT”) current, the second block generates a complementary-to-absolute-temperature (“CTAT”) current, and the third block generates a nonlinear current in isolation from the generating of the PTAT and CTAT currents. The output circuit combines the PTAT current, CTAT current, and nonlinear current to create an output reference voltage.

The nonlinear current may be proportional to T×ln(T/T0). The first block may include a trimmable resistor for balancing first-order components of the PTAT and CTAT currents. A current DAC may trim the trimmable resistor and the same or different current DAC may compensate for a process-dependent value by trimming an output resistance. The third block may further include a trimmable resistor for adjusting the nonlinear current to cancel out second-order effects of temperature from the PTAT and CTAT currents and/or a BJT with an inaccessible collector terminal. An amplifier, which may include a chopping circuit for chopping its input values, may isolate the nonlinear current. A chopping circuit may chop an output current, and the first block may include a chopping circuit for chopping resistors used to generate the PTAT current.

In another aspect, a method of generating a voltage reference includes generating a proportional-to-absolute-temperature (“PTAT”) current, generating a complementary-to-absolute-temperature (“CTAT”) current, and generating a nonlinear current in isolation from the generating of the PTAT and CTAT currents. The PTAT current, CTAT current, and nonlinear current are combined to create an output reference voltage.

The nonlinear current may be proportional to T×ln(T/T0). A ratio between the PTAT and CTAT currents may be adjusted (by trimming a resistor) to cancel out first-order effects of temperature in the PTAT and CTAT currents. A scaling factor applied to the nonlinear current may be adjusted (by trimming a resistor) to cancel out second-order effects of temperature from the PTAT and CTAT currents. Two parameters (e.g., PTAT currents) may be chopped to reduce a mismatch between circuit components (e.g., resistors). A process-dependent variable may be compensated for by, e.g., trimming an output resistor.

These and other objects, along with advantages and features of the present invention herein disclosed, will become more apparent through reference to the following description, the accompanying drawings, and the claims. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the same parts throughout the different views. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:

FIG. 1A illustrates a conventional first-order-compensating bandgap voltage-reference circuit;

FIG. 1B illustrates a conventional second-order-compensating bandgap voltage-reference circuit;

FIG. 2 illustrates a circuit diagram of an isolating, adjustable bandgap voltage-reference circuit in accordance with an embodiment of the invention;

FIG. 3 illustrates a block diagram of an isolating, adjustable bandgap voltage-reference circuit in accordance with an embodiment of the invention;

FIG. 4 illustrates a transistor-level implementation of an isolating, adjustable bandgap voltage-reference circuit in accordance with an embodiment of the invention;

FIG. 5 illustrates an implementation of a trimming circuit in accordance with an embodiment of the invention;

FIG. 6 illustrates a flowchart for generating an isolating, adjustable bandgap voltage reference in accordance with an embodiment of the invention; and

FIG. 7 illustrates a timing diagram for chopping in accordance with an embodiment of the invention.

DETAILED DESCRIPTION 1. Overview and Methodology

Described herein are various embodiments of methods and systems for generating a reference voltage that corrects for the second-order effects of temperature on the bandgap voltage while isolating the generation of each component of the output voltage and allowing for post-manufacturing adjustment of the “α” coefficient used to generate the second-order component. Three semiconductor devices (e.g., diode-connected BJTs) are used to separately generate a PTAT current, a CTAT current, and a third current proportional to a nonlinear, second-order component of the bandgap's value with respect to temperature. In one embodiment, buffers are used to isolate each device. The “XTI” factor, which may not be correctly identified via simulation alone, may be defined via characterization; once identified, its value is stable and its variation over time may be monitored through further characterization. In one embodiment, the invention uses only substrate-based PNP BJTs; in many CMOS processes, NPN BJTs are unavailable and/or access to the BJT's collector terminal is impossible.

The bandgap reference value of silicon is accessible by measuring the base-emitter voltage (“V_(BE)”) of a diode-connected BJT. This voltage varies nonlinearly in accordance with the second-order term αT ln

$\frac{T}{T_{0}}$

that appears below in Equation (1).

$\begin{matrix} {{V_{BE}(T)} \propto {\alpha \; T\; \ln \frac{T}{T_{0}}}} & (1) \end{matrix}$

In one embodiment, the present invention generates the nonlinear, second-order term of Equation (1) in isolation, scales it, and subtracts it from the current resulting from the sum of the first-order bandgap currents, PTAT and CTAT. Note that, throughout this application, the scaling factors applied to the PTAT and CTAT values are β and γ, respectively, making the sum of the three currents equal to (αT×ln(T/T₀))+(β×PTAT)+(γ×CTAT). In particular, the current based on Equation (1) is used to cancel out a nonlinear component of the generated CTAT current. The value of the α coefficient of V_(BE)(T) in Equation (1) depends at least in part on the temperature dependency of the bias current through the junction of the BJT generating the term. The use of three buffers (in one embodiment, transconductance amplifiers) isolates the three current components PTAT, CTAT and T×ln(T/T₀) from each other.

In one embodiment, a circuit 200 (illustrated in FIG. 2) that implements the present invention includes three blocks or sections: a PTAT block (including a first BJT Q₁) for generating a PTAT current, a CTAT block (including a second BJT Q₂) for generating a CTAT current, and a nonlinear block (including a third BJT Q₃) for generating a nonlinear current proportional to T×ln(T/T₀). Each block is explained in greater detail below; in summary, the PTAT block generates a PTAT current I₄/I₅ by adjusting the magnitudes of currents I₄ and I₅ and/or by trimming a resistor R₁; the CTAT block generates a CTAT current I₆ by buffering a negative-temperature-dependent voltage V(B) on a node B (which is the V_(BE) of the second transistor Q₂) onto a resistor R₂, thereby generating the current I₆ as V(B)/R₂; and the nonlinear block generates the nonlinear current I₈ by subtracting V(B) from a voltage V(D) on a node D (which is the V_(BE) of the third transistor Q₃), wherein V_(BE)(Q₃)>V_(BE)(Q₂), thereby creating a current proportional to T×ln(T/T₀) through a resistor R₃. This resistor R₃ may be adjusted to achieve the needed “α” coefficient value needed to cancel the non-linear component from the current flowing through R₂, resulting in a pure CTAT current I₇. The output reference voltage may be generated by summing the currents I₄+I₅+I₇ on node D (wherein current I₇ is the sum of I₆ and I₈, as computed on node C), mirroring the current, and passing the mirrored current through an output resistor R₄, as explained in greater detail below. R₄ may be matched to the other resistors R₁, R₂, R₃.

2. PTAT Current Generation

The PTAT currents I₄, I₅ may be generated by applying a voltage ΔV_(BE) (i.e., the difference between the base-emitter voltages V_(BE) of the first transistor Q₁ and the second transistor Q₂) across R₁. The amplifier A₁ forces its two inputs (nodes A and B) to be the same voltage in accordance with its design parameters. Currents I₄ and I₅ are forced to be equal by equivalent resistors R_(A) and R_(B) (because node D is common to both resistors R_(A) and R_(B), their voltage drops V(DA) and V(DB) are equal, and therefore their currents I₄ and I₅ are equal). The gain of the first amplifier A₁ may be large enough such that any difference V(AB) that does develop between its inputs A, B (i.e., any difference that breaks the assumption that V(A)=V(B)) produces an error less than the maximum tolerable error for the circuit 200. In one embodiment, the overall accuracy of the circuit 200 depends not on the absolute value but on the relative mismatch between R_(A) and R_(B), which may be minimized via chopping (as explained in greater detail below), sizing, and/or layout technique.

Assuming N to be the ratio in size/strength between the first transistor Q₁ and the second transistor Q₂ and assuming the PTAT currents I₄ and I₅ to be equal for the reason described above, the difference between the respective V_(BE) voltages of transistors Q₁ and Q₂ is shown below in Equation (2).

$\begin{matrix} {{\Delta \; {V_{BE}(T)}} = {\frac{KT}{q}\ln \; N}} & (2) \end{matrix}$

In accordance with Equation (2), the resulting currents I₄ and I₅ are shown below in Equation (3).

$\begin{matrix} {{I_{4}(T)} = {{I_{5}(T)} = {{\frac{KT}{{qR}_{1}}\ln \; N} = {{\left( {\frac{K}{{qR}_{1}}\ln \; N} \right)T} = {\beta \; T}}}}} & (3) \end{matrix}$

Thus, the PTAT currents are directly proportional to the temperature T in accordance with a scaling factor β.

3. CTAT Current Generation

To generate the CTAT component, the voltage V(B) on node B is buffered via a second amplifier A₂. The buffered voltage may be transformed into a current I₆ via a resistor R₂, which is of the same kind as, and sized proportionally to, the other resistors R₁, R₃, R₄. An NMOS transistor M₁ may be configured as a source-follower circuit between the second amplifier A₂ and the resistor R₂; the transistor M₁ may have its bulk and source terminals connected together in order to avoid or reduce asymmetric-leakage current injection from the source-bulk NP junction (which varies over temperature and may affect the accuracy of the circuit 200 if the transistor M₁ is not so configured).

Given the above configuration for the generation of the CTAT current, Equation (4) describes the voltage for a BJT base-to-emitter PN junction.

$\begin{matrix} {\left. V_{BE} \right|_{T} = {E_{G} - {\left( {E_{G} - V_{{{BE}@T}\; 0}} \right)\frac{T}{T_{0}}} - {\left( {{XTI} - \delta} \right)\frac{KT}{q}\ln \frac{T}{T_{0}}}}} & (4) \end{matrix}$

wherein V_(BE@T0) is the voltage at temperature T₀, E_(G) is the bandgap voltage, XTI is a process dependent parameter, and δ is a variable parameter equal either to −1 (for positive-temperature-coefficient bias current), +1 (for negative-temperature-coefficient bias current), or 0 (for constant over-temperature bias current).

Given the value for I₅ given in Equation (3), the voltage V(B) on node B has a temperature dependency described in Equation (5).

$\begin{matrix} {V_{B} = {E_{G} - {\left( {E_{G} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}} - {\left( {{XTI} - 1} \right)\frac{KT}{q}\ln \frac{T}{T_{0}}}}} & (5) \end{matrix}$

Equation (5) includes a constant term E_(G), an inversely-proportional-to-temperature term (E_(G)−V_(B@T0))T/T₀ (which is the CTAT term), and a nonlinear term (XTI−1)*KT/q*ln(T/T₀). The CTAT term may be scaled and added to Equation (3) to thereby offset and eliminate both it and the PTAT term. A nonlinear current may be generated, as explained in greater detail below, to offset the nonlinear term in Equation (5).

4. Nonlinear Current Generation

The third transistor Q₃ is biased with a replica of the output current I₄+I₅+I₇ (via use of a current mirror). The node D′ connected to the third transistor is therefore at the same potential as the node D that sums the currents I₄, I₅, I₇ (in other words, V(D)=V(D′)). The voltage V(D) is, to first approximation, constant in temperature, which results in a voltage V_(D) given below by Equation (6).

$\begin{matrix} {V_{D} = {E_{G} - {\left( {E_{G} - V_{{D@T}\; 0}} \right)\frac{T}{T_{0}}} - {{XTI}\frac{KT}{q}\ln \frac{T}{T_{0}}}}} & (6) \end{matrix}$

The difference between the voltages V(D) and V(B) is transformed into a current I₈ via the third amplifier A₃ and the resistor R₃ (which is, as mentioned above, of the same kind as and sized proportionally to R₁, R₂, and R₄). The resulting currents I₆ and I₈ are given below by Equations (7) and (8).

$\begin{matrix} {\mspace{79mu} {I_{6} = \frac{E_{G} - {\left( {E_{G} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}} - {\left( {{XTI} - 1} \right)\frac{KT}{q}\ln \frac{T}{T_{0}}}}{R_{2}}}} & (7) \\ {I_{8} = {\frac{\begin{pmatrix} {E_{G} - {\left( {E_{G} - V_{{D@T}\; 0}} \right)\frac{T}{T_{0}}} -} \\ {{XTI}\frac{KT}{q}\ln \frac{T}{T_{0}}} \end{pmatrix} - \begin{pmatrix} {E_{G} - {\left( {E_{G} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}} -} \\ {\left( {{XTI} - 1} \right)\frac{KT}{q}\ln \frac{T}{T_{0}}} \end{pmatrix}}{R_{3}} = \frac{{\left( {V_{{D@T}\; 0} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}} - {\frac{KT}{q}\ln \frac{T}{T_{0}}}}{R_{3}}}} & (8) \end{matrix}$

Note that the nonlinear current I₆, does not affect the results of Equations (5) and (6) due at least in part to the presence of the amplifiers A₂ and A₃ and its isolation from the generation of currents I₄ and I₅. Furthermore, because the amplifier A₃ isolates the current I₈, that current does not affect the output current I₃.

A second NMOS transistor M₂ may be configured as a second source follower; its body effect is absorbed by its configuration. The gain of the third amplifier A₃ is, in one embodiment, large enough to guarantee that its input voltage V(DF) is much less than the maximum error allowed to achieve the target precision of the circuit 200 (like the first and second amplifiers A₁, A₂). The resistance of the resistor R₃ may be changed by tapping it using an input of the third amplifier A₃.

The voltage V(D) on node D has a logarithmic relationship with I₃, so the current I₃ need not be precisely matched with the sum of the currents I₄, I₅, I₇. The resulting current I₇, on node C, is given by the sum of currents I₆ and I₈ in accordance with Equation (9).

$\begin{matrix} {I_{7} = {\frac{E_{G} - {\left( {E_{G} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}} - {\left( {{XTI} - 1} \right)\frac{KT}{q}\ln \frac{T}{T_{0}}}}{R_{2}} - \frac{{\left( {V_{{D@T}\; 0} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}} - {\frac{KT}{q}\ln \frac{T}{T_{0}}}}{R_{3}}}} & (9) \end{matrix}$

The overall current I₉ resulting from summing currents I₄, I₅, I₇ is given by Equation (10),

$\begin{matrix} {I_{9} = {{\frac{E_{G} - {\left( {E_{G} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}} - {\left( {{XTI} - 1} \right)\frac{KT}{q}\ln \frac{T}{T_{0}}}}{R_{2}} - \frac{{\left( {V_{{D@T}\; 0} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}} - {\frac{KT}{q}\ln \frac{T}{T_{0}}}}{R_{3}} + {2\frac{KT}{{qR}_{1}}\ln \; N}} = {{\left( {2\frac{K}{{qR}_{1}}\ln \; N} \right)T} + {\beta \frac{T}{T_{0}}} + {\alpha \; T\; \ln \frac{T}{T_{0}}}}}} & (10) \end{matrix}$

in which I₄ and I₅ are assumed to be equal.

It may be derived that by satisfying the relationship shown in Equation (11),

$\begin{matrix} {\frac{\left( {{XTI} - 1} \right)}{R_{2}} = {\left. \frac{1}{R_{3}}\rightarrow\frac{R_{2}}{R_{3}} \right. = {{XTI} - 1}}} & (11) \end{matrix}$

the coefficient “α” shown in Equation (10) becomes zero, which in turn simplifies Equation (10) into the form shown below in Equation (12).

$\begin{matrix} {I_{9} = {{{2\frac{K}{{qR}_{1}}\ln \; N} + \frac{E_{G} - {\left( {E_{G} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}}}{R_{2}} - \frac{\left( {V_{{D@T}\; 0} - V_{{B@T}\; 0}} \right)\frac{T}{T_{0}}}{R_{3}}} = {\frac{E_{G}}{R_{2}} + {\gamma \; T} + {\beta \; T}}}} & (12) \end{matrix}$

The coefficients β and γ (related to PTAT and CTAT, respectively) are, in first approximation, given by Equation (13).

$\begin{matrix} {\beta = {{{- \left( {\frac{V_{{D@T}\; 0}}{R_{3}} + \frac{E_{G}}{R_{2}}} \right)}\frac{1}{T_{0}}\mspace{14mu} {and}\mspace{14mu} \gamma} = {{2\frac{K}{{qR}_{1}}\ln \; N} + {\left( \frac{R_{2} + R_{3}}{R_{2}R_{3}} \right)\frac{V_{{B@T}\; 0}}{T_{0}}}}}} & (13) \end{matrix}$

Given the process-dependent XTI value in Equation (11), the ratio between R₁ and R₂ may be determined by equating the γ and β coefficients given in Equation (13), as shown below in Equation (14). This ratio may be used to choose relative sizes for R₁ and R₂ to achieve a constant-over-temperature reference output.

$\begin{matrix} {\frac{R_{1}}{R_{2}}2\frac{{KT}_{0}}{q}\frac{1}{{E_{G}\left( {{XTI} - 1} \right)} + V_{{D@T}\; 0} - {V_{{B@T}\; 0}{XTI}}}\ln \; N} & (14) \end{matrix}$

5. Additional Features

A block diagram of another circuit 300 configured in accordance with an embodiment of the current invention is shown in FIG. 3. The circuit 300, like the circuit 200 shown in FIG. 2, includes transistors Q₁, Q₂, Q₃ (shown here as diodes) for generating the PTAT, CTAT, and nonlinear currents, respectively, and amplifiers A₁, A₂, A₃ for isolating generation of the currents. Other parts of the circuit 300 are analogous to similarly named parts of the circuit 200 shown in FIG. 2, such as the PTAT currents I₄/I₅, the CTAT current I₇, and the nonlinear current I₈.

The circuit 300 includes chopping elements 302, 304 to reduce mismatch between various components in the circuit. “Chopping” refers to a technique for averaging or balancing two (or more) similar currents, voltages, or components to reduce or eliminate any discrepancies between them; it works by periodically swapping and re-swapping the chosen parameters. For example, in the circuit 300, currents I₄ and I₅ are, ideally, identical, but a mismatch between resistors R_(A) and R_(B) (among other reasons) may create a difference between them. The chopping element 304 draws current I₄ from resistor R_(A) and current I₅ from resistor R_(B) during the first half of a period T (as would have been the case had there been no chopping element 304). During the second half of the period T, however, the chopping element 304 swaps the currents such that current I₄ is drawn from resistor R_(B) and current I₅ is drawn from resistor R_(A). Thus, over many periods T, the input to the second amplifier A₂ (for example) averages between the currents I₄ and I₅, and any differences between the currents is averaged. The chopping element 304 thus reduces the matching requirements and thus the sizing of resistors R_(A) and R_(B). Chopping element 302 similarly chops currents I₁ and I₂; this chopping may help maintain a close match between the summed currents I₄+I₅+I₇ and the output current I₃, thus easing the design requirements for precision of the current mirrors (i.e., reducing their size).

The amplifiers A₁, A₂, A₃ may similarly chop their input signals to attenuate any temperature- or process-dependent effects on the amplifiers, thus reducing any input offset. This additional boost to the precision of the amplifiers A₁, A₂, A₃ may ease the maximum input offset allowed for the amplifiers, thereby decreasing their size. The chopping of the amplifiers A₁, A₂, A₃ (or of the chopping elements 302, 304) may introduce a frequency component into the operation of the circuit 300; this frequency component, however, may be filtered by various techniques known in the art (e.g., sampling/averaging the reference value at a specific frequency or low-pass filtering the frequency component with passive or active filters) or may be inherently filtered by another circuit or circuits using/interfacing with the reference circuit 300 (i.e., the frequency component may be too fast for those other circuits to even detect it).

In one embodiment, the chopping of the amplifiers A₁, A₂, A₃ occurs at the same frequency. The first 302 and/or second chopping elements 304 may run at a fraction of that frequency (e.g., half) in order to, e.g., avoid working against the chopping of the first amplifier A₁. As described above, the chopping of the amplifiers A₁, A₂, A₃ may reduce their sizes, while the second chopping element 304 (i.e., chopping of R_(A)/R_(B)) may increase the performance (i.e., accuracy) of the bandgap circuit 300 for a given size (or, correspondingly, reduce the size requirement for a given accuracy).

The circuit 300 further includes a startup circuit 306 to assure that it starts properly when the power supply is ramped from zero up to its nominal operating value. The startup circuit 306 pulls node J toward ground when the output voltage V_(out) is below a certain threshold, V_(STUP); when V_(out)>V_(STUP), the startup circuit 306 releases node J, and V_(out) continues to rise toward its steady-state voltage value.

FIG. 4 illustrates another transistor-level circuit 400 implementing another embodiment of the current invention that includes one method of trimming the resistor R₁. The resistor R₁ may be trimmed to match the needed ratio between PTAT and CTAT (in accordance with Equation (14)) for the first-order temperature compensation. In one embodiment, a current DAC IDAC₁ is used to trim resistor R₁, thereby avoiding any parasitic resistance in the path of the current I₄ flowing through the resistor R₁ (which would result in a voltage drop having a temperature coefficient different from the voltage across R₁). The use of transistor-based switches, for example, to short or insert parts of R₁ would create such a situation and introduce a different temperature coefficient into the circuit 200.

Instead, the current DAC IDAC₁ adjusts the apparent value of Rt. In order to raise the apparent value of R₁, IDAC₁ injects a PTAT current I₁₀ in node A and subtracts the same amount of current I₁₀ from node G. Therefore, the voltage drop between node A and G is given by Equation (15). The apparent value of R₁ may be lowered in a similar fashion.

ΔV _(AG) =R ₁ I ₄ +R ₁ I ₁₀ =R ₁(I ₄ +I ₁₀)  (15)

The effective resistance of the resistor R₁ may thus be expressed by Equation (16).

$\begin{matrix} {R_{1\; {effective}} = {\frac{\Delta \; V_{AG}}{I_{4}} = {\frac{R_{1}\left( {I_{4} + I_{10}} \right)}{I_{4}} = {R_{1}\left( {1 + \frac{I_{10}}{I_{4}}} \right)}}}} & (16) \end{matrix}$

Despite the use of the current DAC IDAC₁ and the injected/subtracted current I₁₀, the current flowing into the first transistor Q₁ is still I₄.

A second current DAC IDAC₂ may also be used. If the XTI value determined by simulation and used to design the circuit 400 differs from the actual, measured value of XTI determined after the circuit has been manufactured, the value of resistor R₄ may be trimmed to adjust the final output voltage V_(out). The second current DAC IDAC₂ thus compensates for any possible discrepancy in XTI in addition to compensating for any mismatch between R₄ and R₁, R₂, or R₃ (which may introduce a gain error in the output V_(out)) and/or any mismatch in the current mirrors. In some embodiments, a filter capacitor C₁ is used to compensate the first amplifier A₁ and to low-pass filter any frequencies injected into the circuit 400 by the chopping elements 302, 304. Cascode devices M3-M6 may be used to improve current-matching between the blocks of the circuit 400.

One embodiment of the trimmable resistor R₃ (used, as described above, to adjust the α coefficient and cancel out the second-order temperature component) is shown in the circuit 500 of FIG. 5. The total resistance of the resistor R₃ is divided into sections, and the tap input at node F is connected to one of the points between or adjacent to the sections by a switching network 502, which may use MOS transistors as the switches. This implementation 500 does not insert any switches between the end nodes E, H of the resistor, thereby preventing any insertion of a MOS-based temperature dependency into the resistance R₃. Any leakage current from the switches 502 may be compensated by I₈ and thus not affect I₇. The switches 502 may be programmed after manufacture of the circuit 500 via a programmable control register (accessible via, for example, a JTAG port), by blowing fuses, or by any other means known in the art.

FIG. 6 illustrates a method 600 for generating a reference voltage. A PTAT current is generated in a first step 602, and a CTAT current is generated in a second step 604. In a third step 606, a nonlinear current, proportional to T×ln(T/T₀), is generated in isolation from the generating of the PTAT and CTAT currents. As explained above, the generation in isolation is defined by the magnitude of the nonlinear current having no effect on the PTAT and CTAT currents, and vice versa. In a fourth step 608, the currents are combined to create an output reference voltage.

FIG. 7 illustrates additional chopping schemes 700 that may be used in embodiments of the current invention. A first switching frequency 702 may be used to supply the chopping for the amplifiers A₁, A₂, A₃ between their inputs A+ and A−. A second frequency 704, which is one-half of the first switching frequency 704, may be used by the second chopping unit 304 to chop the resistors R_(A), R_(B). In one embodiment, a third frequency 706 is used by the first chopping unit 302 to chop the currents I₁ and I₂; this third frequency 706 may be one-half of the second frequency 704 and one-quarter of the first frequency 702. In another embodiment, the currents I₁ and I₂ are chopped together with the currents I₃ and I₁₁ in accordance with the fourth frequency 708. In this embodiment, the four currents are rotated in a first phase I′, I₂, I₃, I₁₁, a second phase I₁₁, I₁, I₂, I₃, a third phase I₃, I₁₁, I₁, I₂, and a fourth phase I₂, I₃, I₁₁, I₁ to further improve the performance of the circuit 300.

Certain embodiments of the present invention were described above. It is, however, expressly noted that the present invention is not limited to those embodiments, but rather the intention is that additions and modifications to what was expressly described herein are also included within the scope of the invention. Moreover, it is to be understood that the features of the various embodiments described herein were not mutually exclusive and can exist in various combinations and permutations, even if such combinations or permutations were not made express herein, without departing from the spirit and scope of the invention. In fact, variations, modifications, and other implementations of what was described herein will occur to those of ordinary skill in the art without departing from the spirit and the scope of the invention. As such, the invention is not to be defined only by the preceding illustrative description. 

What is claimed is:
 1. A system for generating a voltage reference, the system comprising: a first block for generating a proportional-to-absolute-temperature (“PTAT”) current; a second block for generating a complementary-to-absolute-temperature (“CTAT”) current; a third block for generating a nonlinear current in isolation from the generating of the PTAT and CTAT currents; and an output circuit for combining the PTAT current, CTAT current, and nonlinear current to create an output reference voltage.
 2. The system of claim 1, wherein the nonlinear current is proportional to T×ln(T/T₀).
 3. The system of claim 1, wherein the first block comprises a trimmable resistor for balancing first-order components of the PTAT and CTAT currents.
 4. The system of claim 2, further comprising a current DAC for trimming the trimmable resistor.
 5. The system of claim 1, further comprising a current DAC for compensating for a process-dependent value by trimming an output resistance.
 6. The system of claim 1, wherein the third block further comprises a trimmable resistor for adjusting the nonlinear current to cancel out second-order effects of temperature from the PTAT and CTAT currents.
 7. The system of claim 1, wherein the third block further comprises a BJT with an inaccessible collector terminal.
 8. The system of claim 1, wherein an amplifier isolates the nonlinear current and wherein the amplifier comprises a chopping circuit for chopping its input values.
 9. The system of claim 1, wherein the first block comprises a chopping circuit for chopping resistors used to generate the PTAT current.
 10. The system of claim 1, further comprising a chopping circuit for chopping an output current.
 11. A method of generating a voltage reference, the method comprising: generating a proportional-to-absolute-temperature (“PTAT”) current; generating a complementary-to-absolute-temperature (“CTAT”) current; generating a nonlinear current in isolation from the generating of the PTAT and CTAT currents; and combining the PTAT current, CTAT current, and nonlinear current to create an output reference voltage.
 12. The method of claim 11, wherein the nonlinear current is proportional to T×ln(T/T₀).
 13. The method of claim 11, further comprising adjusting a ratio between the PTAT and CTAT currents to cancel out first-order effects of temperature in the PTAT and CTAT currents.
 14. The method of claim 12, wherein adjusting the ratio comprises trimming a resistor.
 15. The method of claim 11, further comprising adjusting a scaling factor applied to the nonlinear current to cancel out second-order effects of temperature from the PTAT and CTAT currents.
 16. The method of claim 15, wherein adjusting the scaling factor comprises trimming a resistor.
 17. The method of claim 11, further comprising chopping two parameters to reduce a mismatch between circuit components.
 18. The method of claim 17, wherein the parameters are PTAT currents and the circuit components are resistors.
 19. The method of claim 11, further comprising compensating for a process-dependent variable.
 20. The method of claim 19, wherein compensating for the process-dependent variable comprises trimming an output resistor. 